1. Field of the Invention
The present invention relates to voltage boosting circuits, and more particularly to a boosting circuit for a wordline clock circuit in a semiconductor memory.
2. Description of the Prior Art
Voltage boosting circuits are described in the prior art in various configurations for a variety of purposes.
U.S. Pat. No. 4,061,929, issued Dec. 6, 1977 to Asano entitled CIRCUIT FOR OBTAINING DC VOLTAGE HIGHER THAN POWER SOURCE VOLTAGE describes a voltage boosting circuit which comprises a plurality of units connected in sequence and each composed of a condenser and a plurality of MOSFETs without any transformer or diode.
U.S. Pat. No. 4,029,973 issued June 14, 1977 to Kobayashi et al entitled VOLTAGE BOOSTER CIRCUIT USING LEVEL SHIFTER COMPOSED OF TWO COMPLEMENTARY MIS CIRCUITS discloses an improvement for a voltage booster circuit. The improvement lies in the use of MISFETs as a switching means in a level converting circuit constructed in a complementary MIS semiconductor integrated circuit and therefore the voltage loss due to the conventional switching means can be prevented.
In U.S. Pat. No. 4,216,390 issued Aug. 5, 1980 to Stewart entitled LEVEL SHIFT CIRCUIT, a gating means, biased to pass current only during signal transitions, transfers binary signals from an input signal source to a latch circuit when the signal source and the latch are operated at similar voltages. Following data transfer, the operating voltage across the latch is increased. The voltage levels of the latch output signals are correspondingly increased but the state to which the latch was set is maintained and there is no steady state current conduction through the gating means.
In U.S. Pat. 4,045,691, issued Aug. 30, 1977 to Asano, also entitled LEVEL SHIFT CIRCUIT, a level shift circuit is disclosed including an inverter connected to a first voltage supply source and supplied with an input pulse. A condenser and a directional switching element are connected in series between the output point of the inverter and one potential point of the first voltage supply source. The input of a first MOS-FET is connected to the output of the inverter while the input of a second MOS-FET is connected to a connection point between the condenser and the directional switching element. The source of the first MOS-FET is connected to a common terminal of first and second voltage supply sources while the source of the second MOS-FET is connected to the other terminal of the second voltage supply source. An output voltage is generated between a common connecting point of the drains of the first and second MOS-FETs and one potential point of the second voltage supply source.
Circuits for generating pulsating potentials and voltage levels outside the range of, and/or of greater magnitude than the operating potential applied to the circuits are described in U.S. Pat. No. 4,000,412, issued Dec. 28, 1976 to Rosenthal et al entitled VOLTAGE AMPLITUDE MULTIPLYING CIRCUITS. Each circuit includes first and second transistors for applying a first voltage to one plate of a capacitor and a second voltage to the other plate of the capacitor, during one time interval. During a subsequent time interval, the first and second transistors are turned off and a third transistor applies the second potential to the one plate of the capacitor. The change in the potential at the one plate of the capacitor is coupled to the other plate of the capacitor at which is produced an output potential outside the range of the first and second voltages. The potential difference between the first voltage and the output potential difference is greater in amplitude than the potential difference between the first and second voltages. The circuit may also include means alternately applying the first voltage and then the output potential to an output point for generating pulsating signals of greater amplitude than the magnitude of the applied potential. The outputs of two or more circuits may be combined to produce direct current (d.c.) levels. Also included are circuits which operate from a pulsating source of operating potential.
U.S. Pat. No. 4,520,463, issued May 28, 1985 to Okumura, describes a memory circuit having an improved address decoder which is operable with a low power consumption and comprises a logic means for decoding a part of address signals provided for a plurality of address lines of a memory cell array, and a plurality of transfer gates provided between the logic means and the address lines, in which one of those transfer gates is made enabled in response to a different part of the address signals thereby to transmit the output signal of the logic means to a selected row line through the enabled transfer gate.
In U.S. Pat. No. 4,574,203, issued Mar. 4, 1986 to Baba, a clock generating circuit is described which includes a switch control circuit controlling a C-MOS circuit including first and second transistors having first and second conductivity types, respectively. Also included in the clock generating circuit is a bootstrap capacitor having a first end connected to the junction between the first and second transistors. The switch circuit includes a third transistor, having the first conductivity type, connected between the gate of the first transistor and the junction between the first and second transistors, and a fourth transistor, having the second conductivity type, connected between the gates of the first and second transistors. The gate of the second transistor is connected to receive an input clock signal and the gates of the third and fourth transistors are connected together to receive a delayed clock signal produced by delaying the input clock signal. The second end of the bootstrap capacitor is connected to receive a further delayed and inverted clock signal. When the delayed clock signal has a first value, the switching circuit connects the gates of the first and second transistors together and an output signal with a first level is produced at the junction of the first and second transistors. When the delayed clock signal reaches a second level, the switching circuit connects the gate of the first transistor to the junction of the first and second transistors and the bootstrap capacitor boosts the output signal to a second level.
Other references in the general field of voltage or level boosting include the following U.S. patents.
U.S. Pat. No. 3,999,081 by T. Nakajima entitled CLOCK-CONTROLLED GATE CIRCUIT issued Dec. 21, 1976.
U.S. Pat. No. 3,982,138 by Luisi et al entitled HIGH SPEED-LOW COST, CLOCK CONTROLLED CMOS LOGIC IMPLEMENTATION issued Sept. 21, 1976.
U.S. Pat. No. 3,947,829 by Y. Suzuki entitled LOGICAL CIRCUIT APPARATUS issued Mar. 30, 1976.
U.S. Pat. No. 3,943,377 by Y. Suzuki entitled LOGICAL CIRCUIT ARRANGEMENT EMPLOYING INSULATED GATE FIELD EFFECT TRANSISTORS issued Mar. 9, 1976.
U.S. Pat. No. 3,852,625 by M. Kubo entitled SEMICONDUCTOR CIRCUIT issued Dec. 3, 1974.
U.S. Pat. 3,801,831 by J. S. Dame entitled VOLTAGE LEVEL SHIFTING CIRCUIT issued Apr. 2, 1974.
U.S. Pat. 4,129,794 entitled ELECTRICAL INTEGRATED CIRCUIT CHIPS issued Dec. 12, 1978.
U.S. Pat. No. 4,398,100 entitled BOOSTER CIRCUIT issued Aug. 9, 1983.
U.S. Pat. No. 4,639,622 entitled BOOSTING WORD-LINE CLOCK CIRCUIT FOR SEMICONDUCTOR MEMORY issued Jan. 27, 1987.
U.S. Pat. No. 4,707,625 entitled SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE FORMED WITH A CMOS CIRCUIT AND A BOOTSTRAP CAPACITOR issued Nov. 17, 1987.